![]() | Name | Last modified | Size | Description |
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![]() | Parent Directory | - | ||
![]() | lab_8.pdf | 2025-03-17 16:37 | 136K | |
![]() | ss_01_digital_abstraction.pptx | 2024-12-31 07:10 | 15M | |
![]() | ss_02_cmos_gates.pptx | 2024-12-31 07:10 | 20M | |
![]() | ss_03_kmaps.pptx | 2024-12-31 07:10 | 1.7M | |
![]() | ss_04_comb_logic_part_1.pptx | 2024-12-31 07:10 | 5.9M | |
![]() | ss_05_sequential_flipped.pptx | 2024-12-31 07:10 | 71M | |
![]() | ss_06_verilog_comb_logic.pptx | 2024-12-31 07:10 | 18M | |
![]() | ss_07_verilog_for_fsms.pptx | 2024-12-31 07:10 | 4.5M | |
![]() | ss_08_iterative_circuits.pptx | 2024-12-31 07:10 | 1.3M | |
![]() | ss_10_adders.pptx | 2024-12-31 07:10 | 1.4M | |
![]() | ss_11_datapath.pptx | 2024-12-31 07:10 | 4.9M | |
![]() | ss_12_digital_systems.pptx | 2024-12-31 07:10 | 5.0M | |
![]() | ss_13_timing.pptx | 2024-12-31 07:10 | 1.2M | |
![]() | ss_14_pipelining.pptx | 2024-12-31 07:10 | 4.3M | |
![]() | ss_15_func.pptx | 2024-12-31 07:10 | 9.7M | |
![]() | ss_16_float.pptx | 2024-12-31 07:10 | 2.9M | |
![]() | ss_17_interfaces.pptx | 2024-12-31 07:10 | 391K | |
![]() | ss_18_arm_etc.pptx | 2024-12-31 07:10 | 363K | |
![]() | syllabus.pdf | 2024-09-28 20:35 | 382K | |